1. Field of the Invention
The present invention relates to a semiconductor device, a nonvolatile semiconductor storage apparatus using the device and a manufacture method of the device, particularly but not limited to a preferable semiconductor device for use in an electrically erasable and programmable read only memory (EEPROM), and the like, a nonvolatile semiconductor storage apparatus using the device and a manufacture method of the device.
2. Description of the Related Art
One type of a conventional nonvolatile semiconductor memory (which is mainly ROM) are various EEPROMs. In such a memory frequently perform data writing, erasing, reading, and the like are performed electrically, and rewritten data is held for a very long time.
In the EEPROM, a cell structure is of a two-layer gate type in which, for example, a floating gate is formed on a transistor channel area via a first gate insulating film, and a control gate is formed on the floating gate via a second insulating film. By thinning a part of the first gate insulating film to such an extent that a tunnel effect occurs, electron injection into and discharge from the floating gate by the tunnel effect is used for information writing and erasing.
FIG. 1 is a plan view showing one example of a memory array of an EEPROM. This EEPROM is disclosed, in Japanese Patent Application Laid-Open No. 147389/1995. FIG. 2 is a sectional view along line A—A of FIG. 1, and FIG. 3 is an equivalent circuit diagram of the memory array of FIG. 1.
This memory array is referred to as an AND type. The main surface of a memory array area in a p-type semiconductor substrate 1 is provided with a buried bit line BD (BD1, BD2, . . . ) consisting of an n+-type semiconductor area and a buried source line BS (BS1, BS2, . . . ), and these buried bit lines BD1, BD2, . . . and buried source lines BS1, BS2, . . . extend parallel to each other along one direction of the memory array and are alternately arranged in the array direction.
A word line W (W1, W2 . . . ) is disposed in a direction crossing at right angles to the buried bit lines BD and buried source lines BS, and a memory cell for storing one bit of information is formed in an area in which the word line W, and a buried bit line BD or a buried source line BS intersect one another.
A block B1 is an area between a select gate SG1 and a common source line SL. A block B1′ is formed similar to the block B1. These blocks are symmetric with respect to the line C in FIG. 1. Select transistors include select gates SG1 and SG1′ respectively and each block is selected according to voltages applied to each select gate.
A memory cell of this memory is constituted of an floating gate transistor 8 comprising a first gate insulating film 2; a floating gate 3; a second gate insulating film 4; a control gate 5 formed integrally with the word line W; a source area 6 integrated with the buried source line BS formed inside the p-type semiconductor substrate 1 and on both sides of the floating gate 5; and a drain area 7 integrated with the buried bit line BD.
An interlayer insulating film 9 is formed on the control gate 5, and a bit line D (D1, D2, . . . ) is connected to a buried bit line BD (BD1, BD2 , . . . ) via a contact hole 10 formed in the interlayer insulating film 9. Moreover, end portions of the buried source lines BS (BS1, BS2, . . . ) are connected to the common source line SL. The common source line SL consists of an n+-type semiconductor area on the main surface of the p-type semiconductor substrate 1. Furthermore, in the main surface of the semiconductor substrate 1, a groove 11 for isolating memory cells connected to the same word line W is formed, and an insulating film 12 is buried in the groove 11.
When a data is written to the memory cell, and for example, when the cell connected to a bit line D1 is a writing cell, and a cell connected to a bit line D2 is a non-writing cell, a voltage of 5 V is applied to the drain area 7 (the buried bit line BD1) of the writing cell, the source area 6 (the buried source line BS1) is grounded (0 V), a high voltage of 10 V is applied to the word line W2 (the control gate 5), and a channel hot electron generated in the drain area 7 (the buried bit line BD1) is injected to the floating gate 3. Therefore, the data is written to the memory cell formed in an area in which the word line W2 and the bit line D1 intersect one another.
Moreover, in order to erase the data written to the writing cell, a negative voltage of −10 V is applied to the word line W2 (control gate 5), the drain area 7 (the buried bit line BD1) is grounded (0 V), a voltage of 5 V is applied to the source area 6 (the buried source line BS1), and an electron is drawn toward the source area 6 (the buried source line BS1) from the floating gate 3 by Fowler-Nordheim (FN) tunneling. Therefore, the data is erased from the memory cell formed in an area in which the word line W2 and the bit line D1 intersect one another.
In the aforementioned conventional memory cell, since source and drain are separated from those of an adjacent cell, incorrect writing to the adjacent cell can be prevented. However, it is very difficult to establish both high integration and low power consumption as described later.
In the conventional memory cell, a writing system by channel hot electron (CHE) injection is used. In this system of passing a current to a channel, and injecting a hot electron generated in the drain area 7 (the buried bit line BD1) to the floating gate 3 by a gate electric field applied to the control gate 5 (the word line W2), injection efficiency is remarkably small, as about 10−7, and a large current of several hundreds of microamperes to several milliamperes is consumed during writing to one cell. Therefore, a burden to the charge pumping circuit is large, and the number of cells to be written at the same time is limited, or a chip size is enlarged since capacitors of the charge pumping circuit must be large.
As a countermeasure, a writing system using FN tunneling in a channel area is proposed.
This is a system of applying the high voltage to the control gate 5 (the word line W2), generating an electric field of 10 to 11 MeV in the first gate insulating film 2, and injecting the electron to the floating gate 3 by FN tunneling. Writing is possible with a small current of several tens to several hundreds of pA per cell, the burden to the charge pumping circuit is small because of a low power consumption, the number of cells to be written at one time can be increased, and capacitors of the charge pumping circuit can be little, so chip size increase can be depressed.
When the writing is performed using the channel FN tunneling, a high voltage of about 19 V is applied to the control gate 5 (the word line W.), and 0 V is applied to the bit line (the buried bit line BD1) of the writing cell. In this case, since the high voltage is uniformly applied to the control gate 5 of the cell connected to one word line, a writing inhibition voltage of about 5 V is applied to the bit line (the buried bit lines BD2, BD3, . . . ) of the non-writing cell to inhibit FN tunneling in the non-writing cell.
In this case, when the drain or the source fails to be separated from the adjacent cell, a bit line potential of 0 V for writing exerts an influence on the adjacent cell (for example, the memory cell formed in an area in which the word line W2 and the bit line D2 intersect one another), and writing is inadvertently performed. Alternatively, another phenomenon disadvantageously occurs in which the writing inhibition voltage also exerts an influence on the adjacent cell and the writing is not performed.
Therefore, when channel FN tunneling writing for realizing the low power consumption is used in the conventional memory cell, it is essential to separate the source and drain of the cell from the source and drain of the adjacent cell, for example, by the isolating groove 11 or the like. However, since the isolation structure itself is large, memory cell size is increased, and it is disadvantageously difficult to raise an integration degree.
Moreover, in the conventional memory cell, because of the presence of the isolation structure, in order to raise the integration degree, the floating gate 3 and the control gate 5 have to be miniaturized. As a result, a large coupling capacity ratio Rc cannot be secured, and it is disadvantageously difficult to realize a low voltage. The coupling capacity ratio Rc is shown below, where a capacity of a tunnel film is C1 and a capacity between the floating gate and the control gate is C2.Rc=C2(C1+C2)
The present invention has been developed in consideration of the aforementioned circumstances, and an object thereof is to provide a semiconductor device, a nonvolatile semiconductor storage apparatus using the device and a manufacture method of the device, in which the occupied area of the semiconductor device can be reduced, operation is possible with low power consumption, and low voltage can be realized.